1. Field of the Invention
The present invention relates to a liquid crystal display and more particularly to a liquid crystal display which prevents miscounting of clock signals entered into a driver circuit such as a segment drive circuit that supplies an image drive voltage to each pixel, thereby eliminating flicker on the screen.
2. Description of the Related Art
A liquid crystal display has a liquid crystal panel which comprises a pair of substrates (liquid crystal substrates), at least one of which is transparent, whose display surface is constructed of an array of fine patterns constituting respective pixels. According to the liquid crystal drive control method, there are two types of liquid crystal displays. One is a passive matrix display using a so-called STN liquid crystal material in which pixels are formed at intersections of a pair of upper and lower stripes of electrodes, and another is an active matrix display in which switching devices such as thin-film transistors are provided for individual pixels.
In the passive matrix type, the liquid crystal panel holds a liquid crystal layer of liquid crystal material between a first substrate having a first electrode group (hereinafter referred to as a segment electrode group) formed in a direction bridging one pair of parallel sides of the substrate forming a rectangular screen, and a second substrate having a second electrode group (hereinafter referred to as a common electrode group) formed in a direction crossing the segment electrode group. The liquid crystal panel also has a first multilayer printed circuit board and a second multilayer printed circuit board. The first multilayer printed circuit board is connected to and applies a pixel drive voltage to the segment electrode group through a plurality of segment drive circuits (or segment drivers), each of which is mounted on a tape carrier pad (or TCP) for every two or more segment electrodes. The second multilayer printed circuit board is connected to and applies a common voltage to the common electrode group through a plurality of common drive circuits (or common drivers), each of which is mounted on the TCP for every two or more common electrodes.
On the second multilayer printed circuit board, drive circuits are mounted thereon. The drive circuit applies an image data voltage to the segment electrodes in response to a line clock signal (line pulse, generally denoted CL1), a pixel clock signal (pixel pulse, generally denoted CL2), and a frame clock signal (frame pulse, generally denoted CL3), all supplied from a host computer side.
The pixel clock signal CL2 is received in from a controller on the host computer side and then supplied at a predetermined level through a buffer circuit to a clock line. The clock line is wired both on the second multilayer printed circuit board and on the first multilayer printed circuit board. The clock line on the first multilayer printed circuit board is connected in parallel to a plurality of segment drivers parallelly. Each of the segment drivers counts the clock signal and applies the image data voltage to predetermined pixels, when a predetermined count value is reached.
FIG. 1 is a schematic diagram showing a conventional liquid crystal display having a liquid crystal panel and multilayer printed circuit boards arranged in this liquid crystal panel. In this liquid crystal display, the screen area of a liquid crystal panel 3 is divided into an upper half and a lower half, which are scanned in parallel. An upper screen area AR1 is driven by a plurality of segment drivers 16A1 to 16AN mounted on TCPs 15A1 to 15AN connecting the liquid crystal panel 3 to a segment substrate 1a. The segment substrate 1a is the first multilayer printed circuit board arranged on the upper side of the panel. A lower screen area AR2 is driven by a plurality of segment drivers 16B1 to 16BN mounted on TCPs 15B1 to 15BN connecting the liquid crystal panel 3 to a segment substrate 1b. The segment substrate 1b is the first multilayer printed circuit board arranged on the lower side of the panel.
On a common substrate 2 as the second multilayer printed circuit board, a connector 11, a buffer circuit 12 and logic control circuits 13a, 13b are mounted. The buffer circuit 12 divides the pixel clock signal CL2, receiving from the controller of the host computer to the connector 11, into two systems of clock line. As described above, the upper screen area AR1 is driven by a plurality of segment drivers 16A1 to 16AN arranged on the upper side of the liquid crystal panel and the lower screen area AR2 is driven by a plurality of segment drivers 16B1, to 16BN arranged on the lower side. The frame clock signal CL3 is a signal to determine the start timing of the screen (vertical synchronization signal) and the line clock signal CL1 is a signal to define the start timing of one horizontal scan (horizontal synchronization signal). Explanations of the operation of these two signals are omitted. Signal lines for the clock signal CL1, the pixel clock signal CL2, and the frame signal clock CL3 are generally disposed on both the first multilayer printed circuit board and the second multilayer printed circuit board, and are connected by joiners 14a, 14b between these printed circuit boards.
FIGS. 2(a) and 2(b) are schematic diagrams showing the configuration of a conventional multilayer printed circuit board on the segment side, with FIG. 2(a) representing a perspective view of an essential portion and FIG. 2(b) representing a cross section of FIG. 2(a) taken along the line 2Bxe2x80x942B.
A segment substrate 1a, which is the first multilayer printed circuit board, is arranged on the upper side of the liquid crystal panel 3 as shown in (a) and connected to the panel through the TCP 15A1, 15A2, . . . 15AN mounting the segment drivers 16A1, 16A2, . . . 16AN.
The liquid crystal display of the aforementioned type is described in, for example, Japanese Patent Laid-Open No. 70601/1985 and Japanese Patent Publication No. 13666/1976.
As shown in FIG. 2(b), the multilayer printed circuit board 1a has six to ten layers of laminated wire 17 and the clock signal wire 18 is generally arranged on a layer a large distance away from the TCP (generally the lower layer of the multilayer printed circuit board 1a). A solder connecting portion 20 of the TCP (TCP 15A1 in the figure) is connected to the pixel clock wire 18 through a through-hole 19. The wire 18 for the pixel clock signal CL2 serves as a high-speed clock signal on the lower layer, and the inventors have discovered that a capacitive component (parasitic capacitance) is formed in the through-hole 19 region, causing reflection.
FIG. 3 shows an equivalent circuit of the clock wire and FIG. 4 shows a waveform of the pixel clock signal CL2. CTCP in FIG. 3 represents an input capacitance of TCP 15A1, . . . 15AN, and CT represents a parasitic capacitance of the clock wire. The clock signal CL2 from the buffer circuit 12 is supplied through the clock wire, and counted by the segment driver 16A1, . . . 6AN, of each TCP. When the count reaches its predetermined value, each of the segment drivers receives data and applies the pixel voltage to the segment wire.
The aforementioned parasitic capacitance CT in the clock wire makes the reflected component (xe2x88x92) so large so that a waveform of the clock signal CL2 is distorted as shown at R in FIG. 4. When the counting by the segment driver 16A1, . . . 16AN is performed at the high-to-low transition of the clock signal waveform, a miscounting is caused by a waveform deformation as shown at R in FIG. 4 which occurs near a threshold VTH Of the high level H and the low level L, resulting in a problem of degraded display quality such as occurrence of flicker on the screen.
An object of the present invention is to overcome the above-described problems experienced with prior art and to provide a high-quality liquid crystal display without occurrence of flicker on the screen.
To achieve the above objective, the present invention arranges a clock signal wire supplying a high-speed clock signal to the liquid crystal drive circuit on a layer close to the surface connected with the TCP in the multilayer printed circuit board. Thereby, the through-hole for connecting the clock signal wire and the TCP can be of a short length which is sufficient to reduce the parasitic capacitance.
In accordance with the present invention, a liquid crystal display device includes a liquid crystal panel having a liquid crystal layer held between a first substrate and a second substrate, the first substrate having a first electrode group extending in a first direction, and the second substrate having a second electrode group extending in a second direction transverse to the first direction, a first multilayer printed circuit board being connected to the first electrode group through a tape carrier pad carrying a plurality of segment drive circuits to apply a pixel drive voltage to the first electrode group, the tape carrier pad being connected with an uppermost wiring layer of the first multilayer printed circuit board, and a second multilayer printed circuit board being connected to the second electrode group through a tape carrier pad carrying a plurality of common drive circuits to apply a common voltage to the second electrode group, the second multilayer printed circuit board having a drive circuit to supply an externally applied pixel clock signal to the segment drive circuits, wherein a high-speed clock signal wire is disposed on one layer of the first multilayer printed circuit board which is located close to an upper surface of the first multilayer printed circuit board so as to reduce parasitic capacitance therealong.
According to a feature of the present invention, a pixel clock signal wire is disposed as the high-speed clock signal wire.
In accordance with the present invention, the through-hole for connecting the clock signal wire and the TCP is shortened and the parasitic capacitance and the reflection noise according thereto are reduced, whereby a liquid crystal display can be obtained without flicker of the displayed images.
In addition to the pixel clock signal wire, this invention can also be applied similarly to other wires such as line clock signal (line pulse CL1) and frame clock signal (frame pulse CL3).
A liquid crystal display device in accordance with the present invention may also include the following features:
(A) first and second substrates having main surfaces thereof opposed to one another so as to constitute a panel;
(B) a liquid crystal layer sealed between the first and second substrates;
(C) a first plurality of electrodes being arranged with respect to the main surface of at least one of the first and second substrates and extending in a first direction;
(D) a second plurality of electrodes being arranged with respect to the main surface of at least one of the first and second substrates and extending in the second direction transverse to the first direction;
(E) a first printed circuit board disposed at a periphery of the panel extending along the second direction, and having a laminated structure of a plurality of printed circuit layers, and having a laminated thickness according to the plurality of printed circuits layers; and
(F) a plurality of first driver circuits juxtaposed between the first printed circuit board and the panel in the second direction, each of the first driver circuits having a voltage supply unit for applying voltages to at least one electrode of the first electrodes corresponding thereto, and at least one control unit for controlling the voltage supply in accordance with at least one clock signal transmitted by the first printed circuit board.
The present invention disposes xe2x80x9ca transmitting line for the at least one clock signalxe2x80x9d on xe2x80x9cone of the printed circuit layers closer to an upper surface of the first printed circuit board the electrical contacts than a center of the laminated thickness of the first printed circuit boardxe2x80x9d, when the first printed circuit board has a plurality of electrical contacts with the first driver circuits on a first printed circuit layer from an upper surface of the first printed circuit board so as to supply the at least one clock signal in parallel to the respective first driver circuits.
When the liquid crystal display device is of the passive matrix type, the first plurality of electrodes is generally arranged with respect to the main surface of the first substrate, and the second plurality of electrodes is generally arranged with respect to the main surface of the second substrate.
When the liquid crystal display device is of the active matrix type, both the first and second plurality of electrodes are generally arranged with respect to the main surface of only one of the first and second substrates.
According to the liquid crystal display structure, the transmitting line for the at least one clock signal may be disposed in the uppermost printed circuit layer of the first printed circuit board.
On the other hand, the transmitting line for the at least one clock signal may be disposed on one of the printed circuit layers other than the uppermost printed circuit layer (the above-identified first printed circuit layer), also. Defining the laminated thickness by the number N of the printed circuit layers except for the uppermost printed circuit layer, the one of the printed circuit layers should be within a number smaller than N/2 from the uppermost printed circuit layer. For example, when the first printed circuit board has at least six printed circuit layers, the transmitting line for the clock signal should be disposed in one of the second and third printed circuit layers from the upper surface of the first printed circuit board. The laminated thickness may be defined by the distance from an upper surface of the first printed circuit layer to a bottom surface of the last printed circuit layer of the laminated first printed circuit board, also.
The present invention has an advantage that when each control unit of the first driver circuits has a sequential logic circuit therein control signals are outputted for controlling voltage applications to the respective electrodes corresponding to the first driver circuit in accordance with the at least one clock signal.
The first printed circuit board may supply a signal other than the at least one clock signal (e.g., the second clock signal having a different frequency from that of the at least one clock signal) supplied in parallel to the respective first circuits by a second transmitting line formed therein. When the second transmitting line disposed on one of the printed circuit layers, on which the transmitting line for the at least one clock signal is disposed, the second transmitting line should be spaced from the transmitting line for the at least one clock signal. Regardless with the positions of these transmitting lines, the transmitting line for the at least one the clock signal should be spaced from the second transmitting line by at least one conductive material electrically connected with neither of these transmitting lines.
If the first printed circuit board has a second transmitting line for a second clock signal having a higher frequency than that of the at least one clock signal, the second clock signal should be disposed on one of the printed circuit layers further from the upper surface of the first printed circuit board than the printed circuit layer on which the transmitting line for the at least one clock signal is disposed. Disposing the second transmitting line on one of the printed circuit layers on which the transmitting line for the at least one clock signal is disposed, the transmitting line for the at least one clock signal should be spaced from the second transmitting line.
In the active matrix type liquid crystal display device having a plurality of switching elements disposed in the panel, the first plurality of electrodes may either apply switching signals to the switching elements (behave as gate lines), or apply voltages to terminals of the switching elements (behave as data lines).
These and other objects, features and advantages of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.